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Ordering number : EN5811
CMOS LSI
LC78624E
Compact Disc Player DSP
Overview
The LC78624E is a CMOS LSI that implements the signal processing and servo control required by compact disc players. Including an EFM-PLL and text decoder, the LC78624E strictly limits functionality to basic signal processing and servo system operation to achieve the best cost-performance balance for low-end players. As basic functions, the LC78624E provides demodulation of the EFM signal from the optical pickup, de-interleaving, error detection and correction, and processes servo commands sent from the control microcontroller.
Functions
* Input signal processing: The LC78624E takes an HF signal as input, digitizes (slices) that signal at a precise level, converts that signal to an EFM signal, and generates a PLL clock with an average frequency of 4.3218 MHz by comparing the phases of that signal and an internal VCO. * Precise reference clock and necessary internal timing generation using an external 16.9344 MHz crystal oscillator * Disk motor speed control using a frame phase difference signal generated from the playback clock and the reference clock * Frame synchronization signal detection, protection and interpolation to assure stable data readout * EFM signal demodulation and conversion to 8-bit symbol data * Subcode data separation from the EFM demodulated signal and output of that data to an external microcontroller * Subcode Q signal output to a microcontroller over the serial I/O interface after performing a CRC error check (LSB first) * Serial output to a microcontroller via the text decoder of the song titles and other text data stored in the Subcode R through W channels of the read-in area * Demodulated EFM signal buffering in internal RAM to handle up to 4 frames of disk rotational jitter
* Demodulated EFM signal reordering in the prescribed order for data unscrambling and de-interleaving * Error detection, correction, and flag processing (error correction scheme: dual C1 plus dual C2 correction) * The LC78624E sets the C2 flags based on the C1 flags and a C2 check, and then performs signal interpolation or muting depending on the C2 flags. The interpolation circuit uses a dual-interpolation scheme. The previous value is held if the C2 flags indicate errors two or more times consecutively. * Support for command input from a microcontroller: commands include track jump, focus start, disk motor start/stop, muting on/off and track count (8 bit serial input) * Built-in digital output circuits. * Arbitrary track counting to support high-speed data access * Zero cross muting * Supports the implementation of a double-speed dubbing function. * Support for bilingual applications. * General-purpose I/O ports: 5 pins
Features
* 64 pin QFP * 5 V single-voltage power supply
Package Dimensions
unit: mm 3159-QFP64E
[LC78624E]
SANYO: QIP64E
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN
20698RM (OT) No. 5811-1/27
LC78624E Equivalent Circuit Block Diagram
Slice level control
VCO clock oscillator clock control
2k x 8-bit RAM
RAM address generator
Synchronization detection EFM demodulation
Interpolation and muting Bilingual
CLV digital servo
C1 and C2 error detection and correction flag processing
Digital output
Subcode separation and CRC checking Microcontroller interface
Subcode text decoder microcontroller interface
Servo command
Generalpurpose ports
Crystal oscillation system timing generator
Pin Assignment
No. 5811-2/27
LC78624E
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Input voltage Output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VIN VOUT Pd max Topr Tstg Conditions Ratings VSS - 0.3 to VSS + 7.0 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to VDD + 0.3 300 -20 to +75 -40 to +125 Unit V V V mW C C
Allowable Operating Ranges at Ta = 25C, VSS = 0 V
Parameter Symbol Conditions VDD, XVDD, VVDD: During normal-speed playback VDD, XVDD, VVDD: During double-speed playback DEFI, COIN, RES, HFL, TES, SBCK, RWC, CQCK, TAI, TEST1 to TEST6, CS, CONT1 to CONT5, SCLK EFMIN DEFI, COIN, RES, HFL, TES, SBCK, RWC, CQCK, TAI, TEST1 to TEST6, CS, CONT1 to CONT5, SCLK EFMIN COIN, RWC: Figure 1 COIN, RWC: Figure 1 SBCK, CQCK: Figures 1, 2 and 3 SBCK, CQCK: Figures 1, 2 and 3 SQOUT, PW: Figures 2 and 3 RWC: Figure 1 WRQ: Figure 2, with no RWC signal SFSY: Figure 3 SFSY: Figure 3 CONT1 to CONT5, RWC: Figure 4 CONT1 to CONT5, RWC: Figure 4 RWC, CQCK: Figure 4 CONT1 to CONT5, RWC: Figure 5 EFMIN: Slice level control XIN: Capacitor-coupled input EFMIN XIN, XOUT DQSY : Figure 6. DQSY : Figure 6. SCLK : Figure 6. SCLK : Figure 6. SCLK : Figure 6. SRDT : Figure 6. SRDT : Figure 6. RES 400 1.5 60 100 100 100 50 50 16.9344 3.3 136 3.7 150 1.0 1.0 10 400 400 400 100 1200 Ratings min 3.0 3.0 0.7 VDD 0.6 VDD 0 0 400 400 400 400 0 1000 11.2 136 400 typ max 5.5 5.5 VDD VDD 0.3 VDD 0.4 VDD Unit
VDD (1) Supply voltage VDD (2) VIH (1) VIH (2) VIL (1) Input low level voltage VIL (2) Data setup time Data hold time High level clock pulse width Low level clock pulse width Data read access time Command transfer time Subcode Q read enable time Subcode read cycle time Subcode read enable time Port input data setup time Port input data hold time Port input clock setup time Port output data delay time Input level Operating frequency range Crystal oscillator frequency Text readout time DQSY pulse width SCLK "low" level pulse width SCLK "high" level pulse width SCLK delay time Text data delay time Reset time tSU tHD tWH tWL tRAC tRWC tSQE tSC tSE tCSU tCHD tRCQ tCDD VIN (1) VIN (2) fop fX tCW tW tWTL tWTH tD1 tD2 tD3 tRES
V V V V V V ns ns ns ns ns ns ms s ns ns ns ns ns Vp-p Vp-p MHz MHz ms s ns ns ns ns ns ns
Input high level voltage
No. 5811-3/27
LC78624E Electrical Characteristics at Ta = 25C, VDD = 5 V, VSS = 0 V
Parameter Current drain Input high level current Symbol IDD IIH (1) IIH (2) Input low level current IIL VOH (1) Output high level voltage VOH (2) VOH (3) VOL (1) Output low level voltage VOL (2) VOL (3) IOFF (1) Output off leakage current IOFF (2) Charge pump output current IPDOH IPDOL VDD, XVDD, VVDD DEFI, EFMIN, COIN, RES, HFL, TES, SBCK, RWC, CQCK: TEST1, SCLK: VIN = VDD TAI, TEST2 to TEST6, CS: VIN = VDD = 5.5 V DEFI, EFMIN, COIN, RES, HFL, TES, SBCK, RWC, CQCK: TAI, TEST1 to TEST6, CS, SCLK: VIN = 0 V EFMO, CLV+, CLV-, V/P, PCK, FSEQ, TOFF, TGL, JP+, JP-, EMPH, EFLG, FSX: IOH = -1 mA TEST7 to TEST8, DQSY, SRDT, LRSY, CK2, ROMXA, C2F, SBSY, PW, SFSY, WRQ, SQOUT, TST11, 16M, 4.2M, CONT1 to CONT5: IOH = -0.5 mA DOUT: IOH = -12 mA EFMO, CLV+, CLV-, V/P, PCK, FSEQ, TOFF, TGL, JP+, JP-, EMPH, EFLG, FSX: IOL = 1 mA TEST7 to TEST8, DQSY, SRDT, LRSY, CK2, ROMXA, C2F, SBSY, PW, SFSY, WRQ, SQOUT, TST11, 16M, 4.2M, CONT1 to CONT5: IOL = 2 mA DOUT: IOL = 12 mA PDO, CLV+, CLV-, JP+, JP-, CONT1 to CONT5: VOUT = VDD PDO, VOUT = 0 V CLV+, CLV-, JP+, JP-, CONT1 to CONT5: -5 64 -96 80 -80 96 -64 25 -5 4 Conditions Ratings min typ 25 max 35 5 75 Unit mA A A A V
4 4.5 1
V V V
0.4
V
0.5 5
V A A A A
PDO: RISET = 68 k PDO: RISET = 68 k
No. 5811-4/27
LC78624E
A09894
Figure 1 Command Input
A09895
Figure 2 Subcode Q Output
A09896
Figure 3 Subcode Output
No. 5811-5/27
LC78624E
A09897
Figure 4 General-Purpose Port Input Timing
A09898
Figure 5 General-Purpose Port Output Timing
A09899
Figure 6 Text Data Output Timing
No. 5811-6/27
LC78624E Pin Functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Symbol DEFI TAI PDO VVSS ISET VVDD FR VSS EFMO EFMIN TEST2 CLV+ CLV- V/P HFL TES TOFF TGL JP+ JP- PCK FSEQ VDD CONT1 CONT2 CONT3 CONT4 CONT5 EMPH C2F DOUT TEST3 TEST4 TEST6 TEST7 LRSY CK2 ROMXA SRDT DQSY SCLK TEST8 XVDD XOUT XIN XVSS SBSY EFLG PW SFSY I/O I I O - AI - AI - O I I O O O I I O O O O O O - I/O I/O I/O I/O I/O O O O I I I O O O O O O I O - O I - O O O O Text data output Text readout enable output Text shift clock input Test output Crystal oscillator power supply. Connections for a 16.9344 crystal oscillator element Crystal oscillator ground. Must be connected to 0 V. Subcode block synchronization signal output C1, C2, single and double error correction monitor pin Subcode P, Q, R, S, T, U, V and W output Subcode frame synchronization signal output. This signal falls when the subcodes are in the standby state. ROMXA output PLL pins Function Defect detection signal (DEF) input. (Must be connected to 0 V when unused.) Test input. A pull-down resistor is built in. Must be connected to 0 V. External VCO control phase comparator output Internal VCO ground. Must be connected to 0 V. PDO output current adjustment resistor connection Internal VCO power supply VCO frequency range adjustment Digital system ground. Must be connected to 0 V. Slice level control EFM signal output EFM signal input Test input. A pull-down resistor is built in. Must be connected to 0 V. Disc motor control output. Three-value output is also possible when specified by microcontroller command. Rough servo/phase control automatic switching monitor output. Outputs a high level during rough servo and a low level during phase control. Track detection signal input. This is a Schmitt input. Tracking error signal input. This is a Schmitt input. Tracking off output Tracking gain switching output. Increase the gain when low. Track jump control output. Three-value output is also possible when specified by microcontroller command. EFM data playback clock monitor. Outputs 4.3218 MHz when the phase is locked. Synchronization signal detection output. Outputs a high level when the synchronization signal detected from the EFM signal and the internally generated synchronization signal agree. Digital system power supply. General-purpose I/O pin 1 General-purpose I/O pin 2 General-purpose I/O pin 3 General-purpose I/O pin 4 General-purpose I/O pin 5 De-emphasis monitor pin. A high level indicates playback of a de-emphasis disk. C2 flag output Digital output. (EIAJ format) Test input. A pull-down resistor is built in. Must be connected to 0 V. Test input. A pull-down resistor is built in. Must be connected to 0 V. Test input. A pull-down resistor is built in. Must be connected to 0 V. Test output L/R clock output Bit clock output Interpolated data output, not ROM output Controlled by serial data commands from the microcontroller. Any of these that are unused must be either set up as input ports and connected to 0 V, or set up as output ports and left open.
Continued on next page.
No. 5811-7/27
LC78624E
Continued from preceding page.
Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Symbol SBCK FSX WRQ RWC SQOUT COIN CQCK RES TST11 16M 4.2M TEST5 CS TEST1 I/O I O O I O I I I O O O I I I Function Subcode readout clock input. This is a Schmitt input. (Must be connected to 0 V when unused.) Output for the 7.35 kHz synchronization signal divided from the crystal oscillator Subcode Q output standby output Read/write control input. This is a Schmitt input. Subcode Q output Command input from the control microcontroller Input for both the command input clock and the subcode readout clock. This is a Schmitt input. Chip reset input. This pin must be set low briefly after power is first applied. Test output. Leave open. (Normally outputs a low level.) 16.9344 MHz output. 4.2336 MHz output Test input. A pull-down resistor is built in. Must be connected to 0 V. Chip select input. A pull-down resistor is built in. Must be connected to 0 V if not controlled. Test input. No pull-down resistor. Must be connected to 0 V.
Note: The same potential must be supplied to all power supply pins, i.e., VDD, VVDD and XVDD.
Pin Applications 1. HF Signal Input Circuit; Pin 10: EFMIN, pin 9: EFMO, pin 1: DEFI, pin 12: CLV+ An EFM signal (NRZ) sliced at an optimal level can be acquired by inputting the HF signal to EFMIN. The LC78624E handles defects as follows. When a high level is input to the DEFI pin (pin 1), EFMO (pin 9) pins (the slice level control outputs) go to the high-impedance state, and the slice level is held. However, note that this function is only valid in CLV phase control mode, that is, when the V/P pin (pin 14) is low. This function can be used in combination with the LA9230M, and LA9240M DEF pins. A09900 Note: If the EFMIN and CLV+ signal lines are too close to each other, unwanted radiation can result in error rate degradation. We recommend laying a ground or VDD shield line between these two lines. 2. PLL Clock Generation Circuit; Pin 3: PDO, pin 5: ISET, pin 7: FR, pin 21: PCK Since the LC78624E includes a VCO circuit, a PLL circuit can Frequency be formed by connecting external R and C (resistors and phase comparator capacitors). ISET is the charge pump reference current, PDO is the VCO circuit loop filter, and FR is a resistor that determines the VCO frequency range. (Reference values) R1 = 68 k, C1 = 0.1 F R2 = 680 , C2 = 0.1 F R3 = 1.2 k
A09901
Code $AC $AD
COMMAND VCO x 2 SET VCO x 1 SET
RES = low q
The VCO x 2 command is an auxiliary command for characteristics guarantee in low-voltage operations. This command supports the low-voltage operations at VDD = 3.0 to 3.6 V.
No. 5811-8/27
LC78624E 3. 1/2 VCO Monitor; Pin 21: PCK PCK is a monitor pin that outputs an average frequency of 4.3218 MHz, which is divided by two from the VCO frequency. 4. Synchronization Detection Monitor; Pin 22: FSEQ Pin 22 goes high when the frame synchronization (a positive polarity synchronization signal) from the EFM signal read in by PCK and the timing generated by the counter (the interpolation synchronization signal) agree. This pin is thus a synchronization detection monitor. (It is held high for a single frame.) 5. Servo Command Function; Pin 54: RWC, pin 56: COIN, pin 57: CQCK Commands can be executed by setting RWC high and inputting commands to the COIN pin in synchronization with the CQCK clock. Note that commands are executed on the falling edge of RWC. Focus start Track jump Muting control Disk motor control Miscellaneous control Track check General-purpose I/O, E/D * One-byte commands
One-byte commands
Two-byte command (RWC set twice) Two-byte commands (RWC set once)
A09902
* Two-byte commands (RWC set twice : For track checking)
A09903
No. 5811-9/27
LC78624E * Two-byte commands (RWC set once: Sets up the general-purpose I/O ports)
A09904
* Command noise rejection
Code $EF $EE Command COMMAND INPUT NOISE REDUCTION MODE RESET THE MODE ABOVE q RES = low
This command reduces the noise on the CQCK clock signal. While this is effective for noise pulses shorter than 500 ns, the CQCK timings tWL, tWH, and tSU, must be set for at least 1 s. 6. CLV Servo Circuit; Pin 12: CLV+, pin 13: CLV-, pin 14: V/P
Code $04 $05 $06 $07 Command DISC MOTOR START (accelerate) DISC MOTOR CLV (CLV) DISC MOTOR BRAKE (decelerate) DISC MOTOR STOP (stop) q RES = low
The CLV+ pin provides the signal that accelerates the disk in the forward direction and the CLV- pin provides the signal that decelerates the disk. Commands from the microcontroller select one of four modes; accelerate, decelerate, CLV and stop. The table below lists the CLV+ and CLV- outputs in each of these modes.
Mode Accelerate Decelerate CLV Stop CLV+ High Low
Pulse output
CLV- Low High
Pulse output
Low
Low
A09905
Note: CLV servo control commands can set the TOFF pin low only in CLV mode. That pin will be at the high level at all other times. Control of the TOFF pin by microcontroller command is only valid in CLV mode.
No. 5811-10/27
LC78624E * CLV mode In CLV mode the LC78624E detects the disk speed from the HF signal and provides proper linear speed using several different control schemes by switching the DSP internal modes. The PWM reference period corresponds to a frequency of 7.35 kHz. The V/P pin outputs a high level during rough servo and a low level during phase control.
Internal mode Rough servo (velocity too low) Rough servo (velocity too high) Phase control (PCK locked) CLV+ High Low PWM CLV- Low High PWM V/P High High Low
* Rough servo gain switching
Code $A8 $A9 Command DISC 8 cm SET DISC 12 cm SET q RES = low
For 8 cm disks, the rough servo mode CLV control gain can be set about 8.5 dB lower than the gain used for 12 cm disks. * Phase control gain switching
Code $B1 $B2 $B3 $B0 Command CLV PHASE COMPARATOR DIVISOR: 1/2 CLV PHASE COMPARATOR DIVISOR: 1/4 CLV PHASE COMPARATOR DIVISOR: 1/8 NO CLV PHASE COMPARATOR DIVISOR USED q RES = low
The phase control gain can be changed by changing the divisor used by the dividers in the stage immediately preceding the phase comparator.
A09906
No. 5811-11/27
LC78624E * CLV three-value output
Code $B4 $B5 Command CLV THREE-VALUE OUTPUT CLV TWO-VALUE OUTPUT (the scheme used by previous products) q RES = low
The CLV three-value output command allows the CLV to be controlled by a single pin.
Two-value output
Three-value output
A09907
* Internal brake modes
Code $C5 $C4 $A3 $CB $CA $CD $CC Command INTERNAL BRAKE ON INTERNAL BRAKE OFF INTERNAL BRAKE CONTROL INTERNAL BRAKE CONTINUOUS MODE RESET CONTINUOUS MODE TON MODE DURING INTERNAL BRAKING RESET TON MODE q q q RES = low
-- Issuing the internal brake-on ($C5) command sets the LC78624E to internal brake mode. In this mode, the disk deceleration state can be monitored from the WRQ pin when a brake command ($06) is executed. -- In this mode the disk deceleration state is determined by counting the EFM signal density in a single frame, and when the EFM signal count falls under four, the CLV- pin is dropped to low. At the same time the WRQ signal, which functions as a brake completion monitor, goes high. When the microcontroller detects a high level on the WRQ signal, it should issue a STOP command to fully stop the disk. In internal brake continuous mode ($CB), the CLV- pin high-level output braking operation continues even after the WRQ brake completion monitor goes high. Note that if errors occur in deceleration state determination due to noise in the EFM signal, the problem may be rectified by changing the EFM signal count from four to eight with the internal brake control command ($A3). -- In TOFF output disabled mode ($CD), the TOFF pin is held low during internal brake operations. We recommend using this feature, since it is effective at preventing incorrect detection at the disk mirror surface.
No. 5811-12/27
LC78624E
A09908
Note: 1. If focus is lost during the execution of an internal brake command, the pickup must first be refocussed and then the internal brake command must be reissued. 2. Since incorrect deceleration state determination is possible depending on the EFM signal playback state (e.g., disk defects, access in progress), we recommend using these functions in combination with a microcontroller. 7. Track Jump Circuit; Pin 15: HFL, pin 16: TES, pin 17: TOFF, pin 18: TGL, pin 19: JP+, pin 20: JP- * The LC78624E supports the two track count modes listed below.
Code $22 $23 Command NEW TRACK COUNT (using the TES/HFL combination) STANDARD TRACK COUNT (directly counts the TES signal) RES = low q
The earlier track count function uses the TES signal directly as the internal track counter clock. To reduce counting errors resulting from noise on the rising and falling edges of the TES signal, the new track count function prevents noise induced errors by using the combination of the TES and HFL signals, and implements a more reliable track count function. However, dirt and scratches on the disk can result in HFL signal dropouts that may result in missing track count pulses. Thus care is required when using this function.
No. 5811-13/27
LC78624E * TJ commands
Code $A0 $A1 $11 $12 $31 $52 $10 $13 $14 $30 $15 $17 $19 $1A $39 $5A $18 $1B $1C $38 $1D $1F $16 $0F $8F $8C $21 $20 Command STANDARD TRACK JUMP NEW TRACK JUMP 1 TRACK JUMP IN #1 1 TRACK JUMP IN #2 1 TRACK JUMP IN #3 1 TRACK JUMP IN #4 2 TRACK JUMP IN 4 TRACK JUMP IN 16 TRACK JUMP IN 32 TRACK JUMP IN 64 TRACK JUMP IN 128 TRACK JUMP IN 1 TRACK JUMP OUT #1 1 TRACK JUMP OUT #2 1 TRACK JUMP OUT #3 1 TRACK JUMP OUT #4 2 TRACK JUMP OUT 4 TRACK JUMP OUT 16 TRACK JUMP OUT 32 TRACK JUMP OUT 64 TRACK JUMP OUT 128 TRACK JUMP OUT 256 TRACK CHECK TOFF TON TRACK JUMP BRAKE TOFF OUTPUT MODE DURING JP PULSE PERIOD RESET TOFF OUTPUT MODE DURING JP PULSE PERIOD q q RES = low q
JP pulse width
A09909
When the LC78624E receives a track jump instruction as a servo command, it first generates accelerating pulses (period a) and next generates deceleration pulses (period b). The passage of the braking period (period c) completes the specified jump. During the braking period, the LC78624E detects the beam slip direction from the TES and HFL inputs. TOFF is used to cut the components in the TES signal that aggravate slip. The jump destination track is captured by increasing the servo gain with TGL. In during TOFF output mode JP pulse period the TOFF signal is held high during the JP pulse generation period. Note: Of the modes related to disk motor control, the TOFF pin only goes low in CLV mode, and will be high during accelerate, stop, and decelerate modes.Note that the TOFF pin can be turned on and off independently by microcontroller issued commands. However, this function is valid only when disk motor control is in CLV mode.
No. 5811-14/27
LC78624E * Track jump modes The table lists the relationships between acceleration pulses (the a period) , deceleration pulses (the b period), and the braking period (the c period).
Command 1 TRACK JUMP IN (OUT) #1 1 TRACK JUMP IN (OUT) #2 1 TRACK JUMP IN (OUT) #3 233 s 0.5 track jump period 0.5 track jump period 0.5 track jump period None 2 track jump period 9 track jump period 18 track jump period 36 track jump period 72 track jump period Standard track jump mode a 233 s 233 s 233 s b 60 ms 60 ms This period does not exist. 60 ms; TOFF is low during the C period. None 60 ms 60 ms 60 ms 60 ms 60 ms c 233 s 0.5 track jump period 0.5 track jump period 0.5 track jump period 1 track jump period 2 track jump period 9 track jump period 18 track jump period 36 track jump period 72 track jump period a 233 s The same time as "a" The same time as "a" The same time as "a" The same time as "a" The same time as "a" The same time as "a" 14 track jump period 28 track jump period 56 track jump period New track jump mode b 60 ms 60 ms This period does not exist. 60 ms; TOFF is low during the C period. 60 ms 60 ms 60 ms 60 ms 60 ms 60 ms c
1 TRACK JUMP IN (OUT) #4
233 s
2 TRACK JUMP IN (OUT) 4 TRACK JUMP IN (OUT) 16 TRACK JUMP IN (OUT) 32 TRACK JUMP IN (OUT) 64 TRACK JUMP IN (OUT) 128 TRACK JUMP IN (OUT)
None 466 s 7 track jump period 14 track jump period 28 track jump period 56 track jump period
256 TRACK CHECK TRACK JUMP BRAKE
TOFF goes high during the period when 256 tracks are passed over. The a and b pulses are not output. There are no a or b periods.
60 ms 60ms
TOFF goes high during the period when 256 tracks are passed over. The a and b pulses are not output. There are no a and b periods.
60 ms 60 ms
Note: 1. As indicated in the table, actuator signals are not output during the 256 TRACK CHECK function. This is a mode in which the TES signal is counted in the tracking loop off state. Therefore, feed motor forwarding is required. 2. The servo command register is automatically reset after one cycle of the track jump sequence (a, b, c) completes. 3. If another track jump command is issued during a track jump operation, the content of that new command will be executed starting immediately. 4. The 1 TRACK JUMP #3 mode does not have a braking period (the C period). Since brake mode must be generated by an external circuit, care is required when using this mode. 5. While there was no braking period (the C period) in the LC78620E/21E for the new track jump command "2 TRACK JUMP IN (OUT)", this has been changed in this LSI, which has a C period of 60 ms.
A09910
The THLD signal is generated by the LA9230M, or LA9240M, and the tracking signal is held during the JP pulse period.
No. 5811-15/27
LC78624E
6. Tracking brake The chart shows the relationships between the TES, HFL, and TOFF signals during the track jump C period. The TOFF signal is extracted from the HFL signal by TES signal edges. When the HFL signal is high, the pickup is over the mirror surface, and when low, the pickup is over data bits. Thus braking is applied based on the TOFF signal being high when the pickup is moving from a mirror region to a data region and being low when the pickup is moving from a data region to a mirror region.
A09911
* JP three-value output
Code $B6 $B7 Command JP THREE-VALUE OUTPUT JP TWO-VALUE OUTPUT (earlier scheme) RES = low
q
The JP three-value output command allows the track jump operation to be controlled from a single pin.
Two-value output
Three-value output
A09912
* Track check mode
Code $F0 $F8 $FF Command TRACK CHECK IN TRACK CHECK OUT TWO-BYTE COMMAND RESET RES = low
q
The LC78624E will count the specified number of tracks plus one when the microcontroller sends an arbitrary binary value in the range 8 to 254 after issuing either a track check in or a track check out command.
A09913
No. 5811-16/27
LC78624E
Note: 1. When the desired track count has been input in binary, the track check operation is started by the fall of RWC. 2. During a track check operation the TOFF pin goes high and the tracking loop is turned off. Therefore, feed motor forwarding is required. 3. When a track check in/out command is issued the function of the WRQ signal switches from the normal mode subcode Q standby monitor function to the track check monitor function. This signal goes high when the track check is half completed, and goes low when the check finishes. The microcontroller should monitor this signal for a low level to determine when the track check completes. 4. If a two-byte reset command is not issued, the track check operation will repeat. That is, to skip over 20,000 tracks, issue a track check 201 command once, and then count the WRQ signal 100 times. This will check 20,000 tracks. 5. After performing a track check operation, use the brake command to have the pickup lock onto the track.
8. Error Flag Output; Pin 48: EFLG, pin 52: FSX
A09914
The FSX signal is generated by dividing the crystal oscillator clock, and is a 7.35 kHz frame synchronization signal. The error correction state for each frame is output from EFLG. The FSX low-level period indicates the C1 correction state, and the high-level period indicates the C2 correction state. The playback OK/NG state can be easily determined from the extent of the high level that appears here. 9. Subcodes P, Q and R to W Output Circuit; Pin 49: PW, pin 47: SBSY, pin 50: SFSY, pin 51: SBCK PW is the subcode signal output pin, and all the codes, P, Q, and R to W can be read out by sending eight clocks to the SBCK pin within 136 s after the fall of SFSY. The signal that appears on the PW pin changes on the rising edge of SBCK. SFSY is a signal that is output for each subcode frame cycle, and the falling edge of this signal indicates standby for the output of the subcode symbol (P to W). Subcode data P is output on the fall of this signal. However, when the text data is read or reset, subcodes cannot be read because the LC78624E is in the text mode. The subcodes can be read by inputting the SW1P ON command.
Code $4E $4F Command SW1P OFF SW1P ON RES = low q
A09915
SBSY is a signal output for each subcode block. This signal goes high for the S0 and S1 synchronization signals. The fall of this signal indicates the end of the subcode synchronization signals and the start of the data in the subcode block. (EIAJ format)
A09916
No. 5811-17/27
LC78624E 10. Subcode Q Output Circuit; Pin 53: WRQ, pin 54: RWC, pin 55: SQOUT, pin 57: CQCK, pin 63: CS
Code $09 $89 Command ADDRESS FREE ADDRESS 1 RES = low
q
Subcode Q can be read from the SQOUT pin by applying a clock to the CQCK pin. Of the eight bits in the subcode, the Q signal is used for song (track) access and display. The WRQ will be high only if the data passed the CRC error check and the subcode Q format internal address is 1*. The microcontroller can read out data from SQOUT in the order shown below by detecting this high level and applying CQCK. When CQCK is applied the DSP disables register update internally. The microcontroller should give update permission by setting RWC high briefly after reading has completed. WRQ will fall to low at this time. Since WRQ falls to low 11.2 ms after going high, CQCK must be applied during the high period. Note that data is read out in an LSB first format. Note: * That state will be ignored if an address free command is input. This is provided to handle CDV applications.
8bits
80bits
A09917
Note: 1. Normally, the WRQ pin indicates the subcode Q standby state. However, it is used for a different monitoring purpose in track check mode and during internal braking. (See the items on track counting and internal braking for details.) 2. The LC78624E becomes active when the CS pin is low, and subcode Q data is output from the SQOUT pin. When the CS pin is high, the SQOUT pin goes to the high-impedance state.
No. 5811-18/27
LC78624E 11. Bilingual Function
Code $28 $29 $2A Command STO CONT Lch CONT Rch CONT RES = low
q
* Following a reset or when a stereo ($28) command has been issued, the left and right channel data is output to the left and right channels respectively. * When an Lch set ($29) command is issued, the left and right channels both output the left channel data. * When an Rch set ($2A) command is issued, the left and right channels both output the right channel data. 12. De-Emphasis; Pin 29: EMPH The preemphasis on/off bit in the subcode Q control information is output from the EMPH pin. When this pin is high, the LC78624E internal de-emphasis circuit operates. 13. C2 Flag Output; Pin 30: C2F C2F output flag information in 8-bit units to indicate data error. 14. Digital Output Circuit; Pin 31: DOUT This is an output pin for use with a digital audio interface. Data is output in the EIAJ format. This signal has been processed by the interpolation and muting circuits. This pin has a built-in driver circuit and can directly drive a transformer.
Code $42 $43 $40 $41 $88 $8B Command DOUT ON DOUT OFF UBIT ON UBIT OFF CDROM-XA ROMXA-RST RES = low
q q
q
* The DOUT pin can be locked at the low level by issuing a DOUT OFF command. * The UBIT information in the DOUT data can be locked at zero by issuing a UBIT OFF command. * The DOUT data can be switched to data for which interpolation and muting processing have not been performed by issuing a CD-ROM XA command. (At this time, the audio output (the ROMXA pin) enters the mute mode.) While a ROMXA-RST command is used to switch to the audio output for which interpolation and muting have been performed. (At this time, audio output (the ROMXA pin) is released from the mute mode.) 15. Mute Control Circuit
Code $01 $03 Command MUTE: 0 dB MUTE: - dB RES = low
q
Inputting the above command mutes the audio level (MUTE - dB). Since zero-cross muting is used, there is very little noise associated with this operation. The IC defines zero cross to be the ranges where the upper 7 bits of the data are all zeros or all ones.
No. 5811-19/27
LC78624E 16. Interpolation Circuit Outputting incorrect audio data that could not be corrected by the error detection and correction circuit would result in loud noises being output. To minimize this noise, the LC78624E replaces the incorrect data with linearly interpolated data based on the correct data on either side of the incorrect data. If one set of C2 flags indicate errors, the above replacement is performed, and if two or more sets of C2 flags indicate errors, the IC holds the previous value. However, when correct data is output following two or more consecutive C2 flags indicating errors, the data point between the correct data and the data output two points previously (the held value) is replaced with a value computed by linearly interpolating those two values.
Data holding the previous value
A09918
17. Audio Data Output; Pin 42: LRSY, Pin 43: CK2, Pin 44: ROMXA The ROMXA pin provides the interpolated audio data, MSB first, synchronized with the edges of the LRSY signal using the following timing.
18. Text Block The text block decodes the song titles and other text data stored in the Subcode R through W channels of the compact disc's read-in area. A data pack consists of 24 symbols (24 x 6 = 144 bits) or 18 bytes (18 x 8 = 144 bits). These 18 bytes consist of a 4byte ID field, 12 bytes of text data, and a 2-byte CRC. The 1-bit result of the CRC check ("H" for OK, "L" of NG) for the pack plus the 16 bytes of ID and text data are available to the microcontroller. The chip indicates the availability of this data with a "L" level pulse (min. 60 s, max. 150 s) from the DQSY pin. When the DQSY pin goes to "L" level, the microcontroller reads this data by supplying 128 clock pulses to the SCLK pin. The time limit for reading this data is 3.3 ms for normal playback and 1.5 ms for double-speed playback. The ID bits tell the microcontroller how to interpret the text data that follows.
No. 5811-20/27
LC78624E 19. General-Purpose I/O Ports; Pin 24: CONT1, Pin 25: CONT2, Pin 26: CONT3, Pin 27: CONT4, Pin 28: CONT5 The LC78624E provides the five CONT1 to CONT5 I/O ports. These are all set to function as input pins after a reset. Unused port pins should be either connected to ground or set to the output port function.
Code $DD $DB $DC
Command PORT READ PORT I/O SET PORT OUTPUT SET
RES = low
PORT I SET
Port data is read in by the PORT READ command in synchronization with the falling edge of the CQCK by the SQOUT pin in the order CONT1 to CONT5. This command is a single-byte command.
A09921
Additionally, these ports can be set up individually to function as control output pins with the PORT I/O SET command. The ports are selected using the lower 5 bits of the 1Byte data. The bits in the data correspond to CONT1 to CONT5 in order starting with the LSB of the 1Byte data. This command is a Two- byte command. (RWC set once)
1 Byte data + $DB PORT I/O SET
dn =1 ... Sets CONTn to be an output pin dn =0 ... Sets CONTn to be an input pin n = 0 to 5
No. 5811-21/27
LC78624E Ports set to be output pins can output high or low levels independently. The lower 5 bits of the 1 Byte data correspond to those ports. The bits in the data correspond to CONT1 to CONT5 in order starting with the LSB of the 1 Byte data. This command is a two-byte command. (RWC set once)
1 Byte data + $DC PORT OUTPUT SET
dn =1 ... Outputs high level signal from the CONTn pin set to output dn =0 ... Outputs low level signal from the CONTn pin set to output 20. Clock Oscillator; Pin 45: XIN, pin 44: XOUT
Code $8E $8D $CE $C2 $C1 OSC ON OSC OFF XTAL 16M NORMAL-SPEED PLAYBACK DOUBLE-SPEED PLAYBACK Command RES = low
q q q
The clock that is used as the time base is generated by connecting a 16.9344 MHz oscillator element between these pins. The OSC OFF command turns off both the VCO and crystal oscillators. The system microcontroller can issue double-speed or normal-speed playback command to specify the playback speed when the application implements double-speed playback system. Recommended oscillators CSA-309 (C = 8 pF) from Citizen Watch CSA16.93MXZ040 (C = 15 pF) from Toyama Murata Seisakusho CSA16.93MXW0C3 (with built-in capacitor) from Toyama Murata Seisakusho
21. 16M and 4.2M Pins; Pin 60: 16M, pin 61: 4.2M The 16M pin outputs the 16.9344 MHz external crystal oscillator 16.9344 MHz buffer signal. The 4.2M pin supplies the LA9230M, or LA9240M system clock, normally outputting a 4.2336 MHz signal. When the oscillator is turned off both these pins will be fixed at either high or low.
A09922
No. 5811-22/27
LC78624E 22. Reset Circuit; Pin 58: RES When power is first applied, this pin should be briefly set low and then set high. This will set the muting to - dB and stop the disk motor.
Constant linear velocity servo Muting control Q subcode address conditions Track jump mode Track count mode OSC Playback speed START 0 dB Address 1 Standard Standard ON Normal speed STOP BRAKE CLV
-
Address free New New OFF Double speed
Setting the RES pin low sets the LC78624E to the settings enclosed in boxes in the table.
A09923
23. Other Pins; Pin 2:TAI, pin 64: TEST1, pin 11: TEST2, pin 32: TEST3, pin 33: TEST4, pin 62: TEST5, pin 59: TST11 These pins are used for testing the LSI's internal circuits. Even though pull-down resistors are built into the TAI and TEST2 to TEST5 input pin circuits, these pins must be connected to 0 V during normal operation. TST11 is an output pin and should normally be left open.
No. 5811-23/27
LC78624E 24. Circuit Block Operating Descriptions * RAM address control The LC78624E incorporates an 8-bit x 2k-word RAM on chip. This RAM has an EFM demodulated data jitter handling capacity of 4 frames implemented using address control. The LC78624E continuously checks the remaining buffer capacity and controls the data write address to fall in the center of the buffer capacity by making fine adjustments to the frequency divisor in the PCK side of the CLV servo circuit. If the 4 frame buffer capacity is exceeded, the LC78624E forcibly sets the write address to the 0 position. However, since the errors that occur due to this operation cannot be handled with error flag processing, the IC applies muting to the output for a 128 frame period.
Position -4 or less -3 -2 -1 0 +1 +2 +3 +4 or more Division ratio or processing Force to 0 589 589 589 588 587 587 587 Force to 0 Decrease ratio Standard ratio Increase ratio
* C1 and C2 Error Correction The LC78624E writes EFM demodulated data to internal RAM to compensate for jitter and then performs the following processing with uniform timing based on the crystal oscillator clock. First, the LC78624E performs C1 error checking and correction in the C1 block, determines the C1 flags, and writes data to the C1 flag register. Next, the LC78624E performs C2 error checking and correction in the C2 block, determines the C2 flags, and writes data to internal RAM.
C1 flag No errors 1 error 2 errors 3 errors or more C2 flag No errors 1 error 2 errors 3 errors or more Error correction and flag processing No correction required * Flag reset Correction * Flag reset Correction * Flag set Correction not possible * Flag set Error correction and flag processing No correction required * Flag reset Correction * Flag reset Depends on C1 flags*1 Depends on C1 flags*2
Note: 1. If the positions of the errors determined by the C2 check agree with the C1 flags, the correction is performed and the flags are cleared. However, if the number of C1 flags is 7 or higher, C2 correction may fail. In this case correction is not performed and the C1 flags are taken as the C2 flags without change. Error correction is not possible if one error position agrees and the other does not. Furthermore, if the number of C1 flags is 5 or under, the C1 check result can be seen as unreliable. Accordingly, the flags will be set in this case. Cases where the number of C1 flags is 6 or more are handled in the same way, and the C1 flags are taken as the C2 flags without change. When there is not even one agreement between the error positions, error correction is, of course, impossible. Here, if the number of C1 flags was 2 or under, data that was seen as correct after C1 correction is now seen as incorrect data. The flags are set in this case. In other cases, the C1 flags are taken as the C2 flags without change. 2. When data is determined to have three or more errors and be uncorrectable, correction is, of course, impossible. Here, if the number of C1 flags was 2 or under, data that was seen as correct after C1 correction is now seen as incorrect data. The flags are set in this case. In other cases the C1 flags are taken as the C2 flags without change
No. 5811-24/27
LC78624E 25. Command Summary Table Blank entry: Illegal command, #: Changed or added command, *: Latching commands (mode setting commands), q: Commands shared with an ASP (LA9220M/30M/31M or other processor), Items in parentheses are ASP commands (provided for reference purposes)
$00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F # * TRACKING OFF 2TJ 1TJ 1TJ 4TJ 16TJ 64TJ 256TC 128TJ 2TJ 1TJ 1TJ 4TJ 16TJ 64TJ IN OUT OUT #1 OUT #2 OUT OUT OUT IN IN #1 IN #2 IN IN IN (ADJ.reset) * MUTE # * MUTE - dB 0 dB $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A $2B $2C $2D $2E $2F * STO CONT * LCH CONT * RCH CONT # # # # * TOFF low in TJ mode * TOFF high in TJ mode * New TRACK COUNT * Old TRACK COUNT $40 $41 $42 $43 $44 $45 $46 $47 $48 $49 $4A $4B $4C $4D $4E $4F SW1P OFF SW1P ON * UBIT ON * UBIT OFF * DOUT ON * DOUT OFF $60 $61 $62 $63 $64 $65 $66 $67 $68 $69 $6A $6B $6C $6D $6E $6F # # # #
* DISC MTR START * DISC MTR CLV * DISC MTR BRAKE * DISC MTR STOP q FOCUS START #1 * ADDRESS FREE #
$10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A $1B $1C $1D $1E $1F
$30 $31 $32 $33 $34 $35 $36 $37 $38 $39 $3A $3B $3C $3D $3E
32TJ 1TJ
IN IN #3
$50 $51 $52 $53 $54 $55 $56 $57 1TJ IN #4
$70 $71 $72 $73 $74 $75 $76 $77 $78 $79 1TJ OUT #4 $7A $7B $7C $7D $7E $7F
32TJ 1TJ
OUT OUT #3
$58 $59 $5A $5B $5C $5D $5E $5F
128TJ
OUT
$3F
Continued on next page.
No. 5811-25/27
LC78624E
Continued from preceding page.
Blank entry: Illegal command, #: Changed or added command, *: Latching commands (mode setting commands), q: Commands shared with an ASP (LA9220M/30M/31M or other processor), Items in parentheses are ASP commands (provided for reference purposes)
$80 $81 $82 $83 $84 $85 $86 $87 $88 $89 $8A $8B $8C $8D $8E $8F * #CDROMXA * ADDRESS 1 # * #ROMXA RST TRACK JMP BRK * OSC OFF * OSC ON * TRACKING ON $A0 $A1 $A2 $A3 $A4 $A5 $A6 $A7 $A8 $A9 $AA $AB $AC $AD $AE $AF #VCO X2 SET #VCO X1 SET * DISC 8 SET * DISC 12 SET * Old TRK JMP * New TRK JMP FOCUS START #2 * Internal BRAKE CONT $C0 $C1 $C2 $C3 $C4 $C5 $C6 $C7 $C8 $C9 $CA $CB $CC $CD $CE $CF # # * Internal BRK-DMC low * Internal BRK-DMC high * TOFF during internal BRAKE * TON during internal BRAKE * Xtal 16M * Internal BRK OFF * Internal BRK ON * Double-speed playback * Normal-speed playback $E0 $E1 $E2 $E3 $E4 $E5 $E6 $E7 $E8 $E9 $EA $EB $EC $ED $EE $EF * Command noise rejecter OFF * Command noise rejecter ON * q TRCK CHECK IN (2BYTE DETECT)
$90
(* F.OFF.ADJ.ST)
$B0
* CLV-PH 1/1 mode
$D0
$F0
$91 $92 $93 $94 $95 $96 $97 $98
(* F.OFF.ADJ.OFF) (* T.OFF.ADJ.ST) (* T.OFF.ADJ.OFF) (* LSR.ON) (* LSR.OF/F.SV.ON) (* LSR.OF/F.SV.OF) (* SP.8CM) (* SP.12CM)
$B1 $B2 $B3 $B4 $B5 $B6 $B7 $B8
* CLV-PH 1/2 mode * CLV-PH 1/4 mode * CLV-PH 1/8 mode * CLV3ST output ON * CLV3ST output OFF * JP3ST output ON * JP3ST output OFF
$D1 $D2 $D3 $D4 $D5 $D6 $D7 $D8
$F1 $F2 $F3 $F4 $F5 $F6 $F7 $F8 * q TRCK CHECK OUT (2BYTE DETECT)
$99 $9A $9B $9C $9D $9E $9F
(* SP.OFF) (* SLED.ON) (* SLED.OFF) (* EF.BAL.START) (* T.SERVO.OFF) (* T.SERVO.ON)
$B9 $BA $BB $BC $BD $BE $BF
$D9 $DA $DB $DC $DD $DE $DF #PORT I/O SET #PORT OUTPUT SET #PORT READ
$F9 $FA $FB $FC $FD $FE $FF q NOTHING * q 2BYTE CMD RST
Note: VCO x 2 SET command should be issued in case of low voltage power supply application.
No. 5811-26/27
LC78624E 27. CD-DSP Functional Comparison
Product Function EFM-PLL RAM Speed Digital output Interpolation Zero-cross muting Level meter peak search Bilingual Digital attenuator Digital filters Digital de-emphasis Generalpurpose port Output Input/ output LC7861NE LC7861KE When paired with an analog ASP 16 K 2!/4! q 4 q -12 dB, - ! ! ! 2fs ! 2 ! ! ! ! ! q ! ! 4.5 to 5.5 V QFP64E LC78621E Built-in VCO FR = 1.2 k 16 K 2! q 4 q -12 dB, - q q q 8fs q 2 ! ! q ! ! q q ! 3.6 to 5.5 V QFP80E LC78622E Built-in VCO FR = 1.2 k 16 K 2! q 2 q - ! q q 4fs q ! 5 ! ! ! ! ! q q 3.0 to 5.5 V QFP64E LC78624E Built-in VCO FR = 1.2 k 16 K 2! q 2 q - ! q ! ! ! ! 5 ! ! ! q ! ! ! 3.0 to 5.5 V QFP64E LC78625E Built-in VCO FR = 1.2 k 16 K 2! q 4 q -12 dB, - q q q 8fs q 2 (4) q q ! ! q q ! 3.0 to 5.5 V QFP80E LC78626E Built-in VCO FR = 5.1 k 16 K 2! q 2 q - ! q q 4fs q ! 1 + (3) ! No need q ! ! q q 3.0 to 5.5 V QFP100E LC78630E Built-in VCO FR = 1.2 k 18 K 4! q 2 q - ! q q 2fs q 2 2 + (4) q q ! ! q q ! 3.6 to 5.5 V QFP80E
VCD support Antishock interface Antishock controller CD text support CD-ROM interface 1 bit D/A converter Lowpass filter Power supply voltage Package
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1998. Specifications and information herein are subject to change without notice. PS No. 5811-27/27

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